Power supplies for electronic devices such as televisions, personal computers (PCs), audio equipment, and personal digital assistants frequently are required to supply DC output power. Increasingly for such applications switched mode power supplies (SMPS) are used. SMPS require a DC input bus voltage, which conventionally is provided by rectifying an AC supply such as a mains supply. However, since rectification is highly non-linear, it produces a high levels of harmonics, and results in a significant degradation of the power factor of the supply. The power factor is the ratio of the real power to the apparent power of the system.
As a result, it is increasingly common to include in power supplies such as SMPS, an input stage to operate as a power factor correction (PFC) stage.
Such PFC stages are useful in ensuring compliance of the application with legal requirements for the control of harmonic components, such as the European Union's regulation EN61000-3-2. They also can be beneficial in ensuring that the application is compliant with minimum power factor requirements such as the mandatory at least 90% power factor for PC supplies under the European Commission's “80+” directive.
In addition to being useful for or required by regulatory purposes, PFCs can be of benefit to the system designer, since they can be capable of providing a single bus voltage from universal mains voltages. Such a feature can be of value, in particular, for devices such as power supplies for laptops which can thereby automatically adjust for varying mains voltages, ranging from for example 100V in Japan to 240 in the UK. Moreover, a subsequent DC/DC converter stages can then be optimised for the specific bus voltage, which can result in either decreased costs or increased efficiencies or both.
Under light load conditions, where the load is less than say 50% of its normal level, a two-stage architecture having a PFC upstream of a DC/DC converter, typically suffers a considerable degradation in efficiency. This is particularly significant for very light loads such as between 1% and 5%, or 5% to 10% of the normal level. Such loads can frequently be encountered for instance, when a desktop pc is running only a word-processing or when a laptop has fully charged battery and the workload for the CPU is low. Since such devices can often be run at these very light loads for a high proportion of the use, the resultant waste of energy can be considerable. The efficiency degradation will be partly due to lower efficiency of the DC/DC converter at light load; however, decreases in efficiency of the PFC circuit are usually even worse.
Considering for the moment, Boundary Conduction Mode (BCM), it will be appreciated that to achieve at high inefficiency, the ratio of the transferred energy per cycle to the losses in that same cycle should be high. At low load, usually this is not the case, for two reasons: firstly, near to the zero crossing of the AC waveform and for low instantaneous input voltage in general, the switching frequency is very high, and yet the amount of transferred energy is low. Switching in this area of the AC voltage waveform is very inefficient—conversely, within each half cycle of the AC waveform, the instantaneous efficiency of a PFC circuit is highest when the instantaneous AC voltage is high. Secondly, at low load the peak inductor current is very low, and thus the influence of ringing time and the switching losses become increasingly dominant, since they are roughly proportional to current and frequency, and lowering of the load results in increasing the switching frequency.
A known way to address the above problems is by the introduction of a frequency clamp. A frequency clamp prevents the switching frequency from exceeding a predetermined value. As the load is decreased, this first becomes effective around the zero crossing of the AC supply. With further decrease in load, the fraction of the half-cycle during which the clamp operates increases. Ultimately, the clamp is active during the complete half cycle. Such frequency clamps are used for instance in NXP Semiconductor's product TEA1750. Such a solution is effective for intermediate levels of load; however it does not adequately address the problem for very low loads, since the ratio of transferred power per cycle to the losses is then the still far from optimal.
European patent application EP-A-0,580,237 relates to control of a PFC by means of adjusting the on-time on the AC half cycle by half cycle basis, but maintaining switching during the full half cycle. Switching around the zero crossing of the mains voltage is still present, and the efficiency loss due to that switching around the zero crossing is thus not resolved.
A second known way of addressing the above problems is to use burst mode operation. In burst mode, the PFC is active only during a certain time period. The period may either be preset or derived from the output voltage. The PFC is switched off at low load, and switched on again when the output voltage of the PFC circuit has dropped to a certain minimum value. Such a method is implemented in NXP Semiconductor's TEA1750 Green-Chip III systems. Although this increases the average efficiency considerably, a major drawback remains for some applications in that the output voltage varies significantly. Although some types of DC/DC converters such as flyback can handle this relatively easily, this is not the case for all converter types. For example LLC converters are less tolerant of input voltage variations. And although it is possible to design such a converter for high input voltage variations, this has a significant influence on the efficiency during normal operation, which materially detracts from one of the major benefits of this type of converter.
Moreover, the above known solutions are limited to the boundary conduction mode (BCM) control, and do not readily carry across to continuous conduction mode (CCM) control.
It would be therefore be desirable to be able to operate a PFC circuit to minimise the loss in efficiency at light load whilst avoiding some of the disadvantages of the known solutions.